A major problem in CMOS/BiCMOS IC design is how to drive a large capacitive load (such as a gate array) from a driver with low input capacitance--i.e., how to make big signals from small ones. Furthermore, it is often convenient to have complementary signal outputs with very low skew in propagation, meaning that the propagation delay for both outputs are substantially the same. This is important in such applications as, for example, generating both clock phases for latches and flip-flops.
The standard CMOS and BiCMOS solution of staging inverters is unsatisfactory due to the propagation delay through each stage and the inherent skew between complementary signals.